RXFE=RXFE_0, TXOF=TXOF_0, RXIDEN=RXIDEN_0, RXFIFOSIZE=RXFIFOSIZE_0, TXFLUSH=TXFLUSH_0, TXEMPT=TXEMPT_0, RXEMPT=RXEMPT_0, RXUF=RXUF_0, RXFLUSH=RXFLUSH_0, TXOFE=TXOFE_0, RXUFE=RXUFE_0, TXFE=TXFE_0, TXFIFOSIZE=TXFIFOSIZE_0
LPUART FIFO Register
| RXFIFOSIZE | Receive FIFO Buffer Depth 0 (RXFIFOSIZE_0): Receive FIFO/Buffer depth = 1 dataword. 1 (RXFIFOSIZE_1): Receive FIFO/Buffer depth = 4 datawords. 2 (RXFIFOSIZE_2): Receive FIFO/Buffer depth = 8 datawords. 3 (RXFIFOSIZE_3): Receive FIFO/Buffer depth = 16 datawords. 4 (RXFIFOSIZE_4): Receive FIFO/Buffer depth = 32 datawords. 5 (RXFIFOSIZE_5): Receive FIFO/Buffer depth = 64 datawords. 6 (RXFIFOSIZE_6): Receive FIFO/Buffer depth = 128 datawords. 7 (RXFIFOSIZE_7): Receive FIFO/Buffer depth = 256 datawords. |
| RXFE | Receive FIFO Enable 0 (RXFE_0): Receive FIFO is not enabled. Buffer is depth 1. 1 (RXFE_1): Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. |
| TXFIFOSIZE | Transmit FIFO Buffer Depth 0 (TXFIFOSIZE_0): Transmit FIFO/Buffer depth = 1 dataword. 1 (TXFIFOSIZE_1): Transmit FIFO/Buffer depth = 4 datawords. 2 (TXFIFOSIZE_2): Transmit FIFO/Buffer depth = 8 datawords. 3 (TXFIFOSIZE_3): Transmit FIFO/Buffer depth = 16 datawords. 4 (TXFIFOSIZE_4): Transmit FIFO/Buffer depth = 32 datawords. 5 (TXFIFOSIZE_5): Transmit FIFO/Buffer depth = 64 datawords. 6 (TXFIFOSIZE_6): Transmit FIFO/Buffer depth = 128 datawords. 7 (TXFIFOSIZE_7): Transmit FIFO/Buffer depth = 256 datawords |
| TXFE | Transmit FIFO Enable 0 (TXFE_0): Transmit FIFO is not enabled. Buffer is depth 1. 1 (TXFE_1): Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. |
| RXUFE | Receive FIFO Underflow Interrupt Enable 0 (RXUFE_0): RXUF flag does not generate an interrupt to the host. 1 (RXUFE_1): RXUF flag generates an interrupt to the host. |
| TXOFE | Transmit FIFO Overflow Interrupt Enable 0 (TXOFE_0): TXOF flag does not generate an interrupt to the host. 1 (TXOFE_1): TXOF flag generates an interrupt to the host. |
| RXIDEN | Receiver Idle Empty Enable 0 (RXIDEN_0): Disable RDRF assertion due to partially filled FIFO when receiver is idle. 1 (RXIDEN_1): Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. 2 (RXIDEN_2): Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. 3 (RXIDEN_3): Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. 4 (RXIDEN_4): Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. 5 (RXIDEN_5): Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. 6 (RXIDEN_6): Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. 7 (RXIDEN_7): Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. |
| RXFLUSH | Receive FIFO/Buffer Flush 0 (RXFLUSH_0): No flush operation occurs. 1 (RXFLUSH_1): All data in the receive FIFO/buffer is cleared out. |
| TXFLUSH | Transmit FIFO/Buffer Flush 0 (TXFLUSH_0): No flush operation occurs. 1 (TXFLUSH_1): All data in the transmit FIFO/Buffer is cleared out. |
| RXUF | Receiver Buffer Underflow Flag 0 (RXUF_0): No receive buffer underflow has occurred since the last time the flag was cleared. 1 (RXUF_1): At least one receive buffer underflow has occurred since the last time the flag was cleared. |
| TXOF | Transmitter Buffer Overflow Flag 0 (TXOF_0): No transmit buffer overflow has occurred since the last time the flag was cleared. 1 (TXOF_1): At least one transmit buffer overflow has occurred since the last time the flag was cleared. |
| RXEMPT | Receive Buffer/FIFO Empty 0 (RXEMPT_0): Receive buffer is not empty. 1 (RXEMPT_1): Receive buffer is empty. |
| TXEMPT | Transmit Buffer/FIFO Empty 0 (TXEMPT_0): Transmit buffer is not empty. 1 (TXEMPT_1): Transmit buffer is empty. |